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6 ghz ultrahigh dynamic range differential amplifier data sheet adl5565 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2011C2013 analog devices, inc. all rights reserved. technical support www.analog.com features 3 db bandwidth of 6 ghz (a v = 6 db) pin strappable gain adjust: 6 db, 12 db, and 15.5 db gain range from 0 db to 15.5 db using two external resistors differential or single-ended input to differential output low noise input stage: nf = 8.7 db at 15.5 db gain low broadband distortion (a v = 6 db) 10 mhz: ?107 dbc (hd2), ?110 dbc (hd3) 100 mhz: ?108 dbc (hd2), ?103 dbc (hd3) 200 mhz: ?82 dbc (hd2), ?87 dbc (hd3) 500 mhz: ?68 dbc (hd2), ?63 dbc (hd3) imd3 of ?112 dbc at 100 mhz center slew rate: 11 v/ns fast settling and overdrive recovery of 2 ns single-supply operation: 2.8 v to 5.2 v power down fabricated using the high speed xfcb3 sige process applications differential adc drivers single-ended-to-differential conversion rf/if gain blocks saw filter interfacing functional block diagram vip2 enbl r f r f vcom vop vip1 v in1 v in2 adl5565 gnd v cc von r g2 r g1 r g1 r g2 09959-001 figure 1. general description the adl5565 is a high performance differential amplifier optimized for rf and if applications. the amplifier offers low noise of 1.5 nv/hz and excellent distortion performance over a wide frequency range making it an ideal driver for high speed 8-bit to 16-bit analog-to-digital converters (adcs). the adl5565 provides three gain levels of 6 db, 12 db, and 15.5 db through a pin strappable configuration. for the single- ended input configuration, the gains are reduced to 5.3 db, 10.3 db, and 13 db. using two external series resistors expands the gain flexibility of the amplifier and allows for any gain selection from 0 db to 15.5 db for a differential input and 0 db to 13 db for a single-ended input. the quiescent current of the adl5565 is typically 70 ma, and when disabled, consumes less than 5 ma with ?25 db of input- to-output isolation at 100 mhz. the device is optimized for wideband, low distortion, and noise performance, giving it unprecedented performance for overall spurious-free dynamic range. these attributes, together with its adjustable gain capability, make this device the amplifier of choice for driving a wide variety of adcs, mixers, pin diode attenuators, saw filters, and multielement discrete devices. fabricated on an analog devices, inc., high speed sige process, the adl5565 is supplied in a compact 3 mm 3 mm, 16-lead lfcsp package and operates over the ?40c to +85c temperature range.
adl5565 data she et rev. d | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 3.3 v specifications ...................................................................... 3 5 v specifications ......................................................................... 6 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 circuit description ......................................................................... 16 basic structure ............................................................................ 16 applications information .............................................................. 17 basic connections ...................................................................... 17 input and output interfac ing ................................................... 18 gain adjustment and interfacing ............................................ 19 adc interfacing ......................................................................... 20 lay out considerations ............................................................... 22 soldering information and recommended pcb land pattern .......................................................................................... 23 evaluation board ........................................................................ 23 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 8 /1 3 rev. c to rev. d changes to features section ............................................................ 1 changes to imd 3 va lue s in table 1 ............................................... 4 changes to imd 3 values in table 2 ............................................... 7 changes to figure14 ....................................................................... 12 changes to figure 15 ...................................................................... 13 1 2 /12 rev. b to rev. c changes to figure 25 ...................................................................... 14 changes to figure 27 and figure 28 ............................................. 15 changes to adc interfacing section, figure 37, and figure 38 ... 2 0 6/12 rev. a to rev. b changes to ordering guide .......................................................... 26 4/12 rev. 0 to rev. a changes to table 3; added thermal resistance section and t able 4 , renumbered sequentially ................................................. 9 deleted solder ing information section ....................................... 23 added soldering information and recommended pcb land pattern section and figure 44 , renumbered sequentially ..................................................................................... 23 updated outline dimensions ....................................................... 26 10/ 11 revision 0: initial version
data sheet adl5565 rev. d | page 3 of 28 specifications 3.3 v specifications v s = 3.3 v, v cm = 1.65 v, r l = 200 ? differential, a v = 6 db, c l = 1 pf differential, f = 1 0 0 mhz, t a = 25c; parameters specified ac - coupled differential input and differential output, unless otherwise noted. table 1 . parameter test conditions /comments min typ max unit dynamic performance ?3 db bandwidth a v = 6 db, v out 1.0 v p -p 6750 mhz a v = 12 db, v out 1.0 v p - p 6500 mhz a v = 15.5 db, v out 1.0 v p -p 6250 mhz bandwidth for 0.1 db flatness v out 1.0 v p -p 1000 mhz gain accuracy 1 db gain supply sensitivity v s 5% 1.9 m db/v gain temperature sensitivity ?40c to +85c 0.35 mdb/c slew rate rise, a v = 15.5 db, r l = 200 ?, v out = 2 v step 11 v/ns fall, a v = 15.5 db, r l = 200 ?, v out = 2 v step 11 v/ns settling time 2 v step to 1% 2 ns overdrive recovery time v in = 4 v to 0 v step, v out 10 mv <3 ns reverse isolation (s12) 70 db input/output characteristics input common - mode range a v = 6 db, 12 db, and 15.5 db 1 .2 to 2 v output common - mode range 1.4 to 1.8 v maximum output voltage swing 1 db compr essed 4 v p -p output common - mode offset referenced to vcc/2 ?100 +20 mv output common - mode drift ?40c to +85c 0.34 mv/c output differential offset voltage ?20 +20 mv cmrr 60 db output differential offset drift ?40c to +85c 1.5 mv/c input bias current 5 a input resistance (differential) a v = 6 db 200 ? a v = 12 db 100 ? a v = 15.5 db 6 7 ? input resistance (single - ended) a v = 5.6 db 158 ? a v = 11.1 db 96 ? a v = 14.1 db 74 ? input capacitance (single - ended) 0 .3 pf output resistance (differential) 10 ? power interface supply voltage 2.8 3.3 5.2 v enb l threshold 1.5 v enb l input bias current enb l h igh 500 n a enbl l ow ? 165 a quiescent current enb l h igh 70 ma enbl l ow 5 ma
adl5565 data she et rev. d | page 4 of 28 parameter test conditions /comments min typ max unit noise/ha rmonic performance 10 mhz second/third harmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 107/ ? 110 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 101/ ? 107 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p ? 106/ ? 112 dbc outp ut ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 48/ ? 100 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 52/ ? 108 dbm/dbc a v = 15.5 db, r l = 200 ? , v out = 2 v p - p composite (2 mhz spacing) + 50/ ? 10 4 dbm/dbc second - order intermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 86 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 86 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 86 db c noise spectral density , rti (nsd) a v = 6 db 2.24 nv/hz a v = 12 db 1.52 nv/hz a v = 15.5 db 1.53 nv/hz noise figure (nf) a v = 6 db 10.24 db a v = 12 db 8.66 db a v = 15.5 db 8.78 db 1 db compression point , rto (op1db) a v = 6 db 13.1 dbm a v = 12 db 12.8 dbm a v = 15.5 db 13.1 dbm 100 mhz second/third harmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 108/ ? 10 3 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 91/ ? 99 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p -p ? 89/ ? 100 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 54/ ? 11 2 dbm /dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 53 / ? 11 0 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 52/ ? 1 08 dbm/dbc second - order intermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 8 5 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 8 5 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 86 db c noise spectral density , rti (nsd) a v = 6 db 2.25 nv/hz a v = 12 db 1.53 nv/hz a v = 15.5 db 1.52 nv/hz noise figure (nf) a v = 6 db 10.27 db a v = 12 db 8.69 db a v = 15.5 db 8.7 db 1 db compression point , rto (op1db) a v = 6 db 13 dbm a v = 12 db 12.8 dbm a v = 15.5 db 12.8 db m
data sheet adl5565 rev. d | page 5 of 28 parameter test conditions /comments min typ max unit 2 0 0 mhz second/third harmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 82/ ? 87 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 72/ ? 86 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p -p ? 71/ ? 86 dbc output ip3/third - order intermod ulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite + 46 / ? 9 6 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite + 46/ ? 9 6 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite + 46/ ? 9 6 dbm/dbc second - order i ntermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 8 5 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 7 3 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 7 0 db c noise spectral density , rti (nsd) a v = 6 db 2.36 nv/hz a v = 12 db 1.64 nv/hz a v = 15.5 db 1.51 nv/hz noise figure (nf) a v = 6 db 10.65 db a v = 12 db 9.25 db a v = 15.5 db 8.49 db 500 mhz second/third harmonic distor tion (hd2/ hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 68/ ? 63 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 56/ ? 62 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p -p ? 57/ ? 63 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite + 34/ ? 7 2 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite + 36/ ? 76 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite + 39/ ? 8 2 dbm/dbc second - order intermodulation distortion (im d 2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 75 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 70 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 70 db c noise spectral density , rti (nsd) a v = 6 db 2.62 nv/hz a v = 12 db 1.57 nv/hz a v = 15.5 db 1.47 nv/hz noise figure (nf) a v = 6 db 11.47 db a v = 12 db 8.93 db a v = 15.5 db 8.07 db
adl5565 data she et rev. d | page 6 of 28 5 v specifications v s = 5.0 v, v cm = 2.5 v, r l = 200 ? differential, a v = 6 db, c l = 1 pf differential, f = 1 0 0 mhz, t a = 25c; parameters specified ac - coupled differential input and differential output, unless otherwise noted. table 2 . parameter test conditions /comments min typ max unit dynamic performance ?3 db bandwidth a v = 6 db, v out 1.0 v p -p 7000 mhz a v = 12 db, v out 1.0 v p -p 6750 mhz a v = 15.5 db, v out 1.0 v p -p 6500 mhz bandwidth for 0.1 db flatness v out 1.0 v p - p 1000 mhz gain accuracy 1 db gain supply sensitivity v s 5% 1.6 m db/v gain temperature sensitivity ? 40c to +85c 0.37 mdb/c slew rate rise, a v = 15.5 db, r l = 200 ?, v out = 2 v step 11 v/ns fall, a v = 15.5 db, r l = 200 ?, v out = 2 v step 11 v/ns settling time 2 v step to 1% 2 ns overdrive reco very time v in = 4 v to 0 v step, v out 10 mv <3 ns reverse isolation (s12) 70 db input/output characteristics input common - mode range a v = 6 db, 12 db, and 15.5 db 1 .2 to 3.8 v output common - mode range 1.4 to 3 v maximum output voltag e swing 1 db compressed 8 v p - p output common - mode offset referenced to vcc/2 ?100 +20 mv output common - mode drift ?40c to +85c 0.4 mv/c output differential offset voltage ?20 +20 mv cmrr 60 db output differential offset drift ?40c to +8 5c 1.5 mv/c input bias current 5 a input resistance (differential) a v = 6 db 200 ? a v = 12 db 100 ? a v = 15.5 db 6 7 ? input resistance (single - ended) a v = 5.6 db 158 ? a v = 11.1 db 96 ? a v = 14.1 db 74 ? input capacitance ( single - ended) 0.3 pf output resistance (differential) 10 ? power interface supply voltage 2.8 5 5.2 v enb l threshold 1.5 v enb l input bias current enb l h igh 1 a enbl l ow ? 250 a quiescent current enb l h igh 80 ma enbl l ow 6 ma
data sheet adl5565 rev. d | page 7 of 28 parameter test conditions /comments min typ max unit noise/harmonic performance 10 mhz second/third harmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 111/ ? 116 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 100/ ? 104 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p ? 105/ ? 1 0 6 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 47/ ? 9 8 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 50/ ? 10 4 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 50/ ? 10 4 dbm/dbc second - order intermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 78 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 86 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 9 1 db c noise spectral density , rti (nsd) a v = 6 db 2.25 nv/hz a v = 12 db 1.54 nv/hz a v = 15.5 db 1.55 nv/hz noise figure (nf) a v = 6 db 10.29 db a v = 12 db 8.77 db a v = 15.5 db 9.04 db 1 db compression point , rto (op1db) a v = 6 db 16.8 dbm a v = 12 db 16.7 dbm a v = 15.5 db 16.6 dbm 100 mhz second/third harmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 108/ ? 10 9 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 92/ ? 103 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p -p ? 89.5/ ? 10 5 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 53/ ? 11 0 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 53/ ? 11 0 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) + 52/ ? 1 08 dbm/dbc second - order intermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 87 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 91 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 8 7 db c noise spectral density , rti (nsd) a v = 6 db 2.28 nv/hz a v = 12 db 1.53 nv/hz a v = 15.5 db 1.52 nv/hz noise figure (nf) a v = 6 db 10.39 db a v = 12 db 8.73 db a v = 15.5 db 8.7 db 1 db compression point , rto (op1db) a v = 6 db 16.8 dbm a v = 12 db 16.5 dbm a v = 15 .5 db 16.4 dbm
adl5565 data she et rev. d | page 8 of 28 parameter test conditions /comments min typ max unit 2 0 0 mhz second/third harmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 82/ ? 87 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 72/ ? 86 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p -p ? 71/ ? 86 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite + 46 / ? 9 6 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite + 46/ ? 9 6 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite + 46/ ? 9 6 dbm/dbc second - order intermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 8 5 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 7 4 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 7 0 db c noise spectral density , rti (nsd) a v = 6 db 2.43 nv/hz a v = 12 db 1.63 nv/hz a v = 15.5 db 1.51 nv/hz noise figure (nf) a v = 6 db 10.88 db a v = 12 db 9.2 db a v = 15.5 db 8.54 db 500 mhz second/third ha rmonic distortion (hd2/hd3) a v = 6 db, r l = 200 ?, v out = 2 v p -p ? 69/ ? 66 dbc a v = 12 db, r l = 200 ?, v out = 2 v p -p ? 56/ ? 65 dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p -p ? 58/ ? 66 dbc output ip3/third - order intermodulation distortion (oip3/imd3) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite + 35/ ? 7 4 dbm/dbc a v = 12 db, r l = 200 ?, v out = 2 v p - p composite + 35/ ? 74 dbm/dbc a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite + 37/ ? 78 dbm/dbc second - order intermodulation distortion (imd2) a v = 6 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 73 db c a v = 12 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 7 5 db c a v = 15.5 db, r l = 200 ?, v out = 2 v p - p composite (2 mhz spacing) ? 7 2 db c noise spectral density , rti (nsd) a v = 6 db 2.64 nv/hz a v = 12 db 1.6 nv/hz a v = 15.5 db 1.48 nv/hz noise figure (nf) a v = 6 db 11.56 db a v = 12 db 9.06 db a v = 15.5 db 8.17 db
data sheet adl5565 rev. d | page 9 of 28 absolute maximum rat ings table 3 . parameter rati ng output voltage swing bandwidth product 20 00 v p -p mhz supply voltage , v cc 5.25 v vip x , vin x v cc + 0.5 v i out max imum 3 0 ma internal power dissipation 525 mw maximum junction temperature 125c operating temperature range ?40c to +100c storag e temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicate d in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 4 lists the junction - to - air thermal re sistance ( ja ) and the junction - to - paddle thermal resistance ( jc ) for the adl5565 . table 4 . thermal resistance package type ja 1 jc 2 unit 16 lfcsp 6 0 12 c/w 1 measu red on analog devices evaluation board. for more information about board layout, see the soldering information and recommended pcb land pattern section. 2 based on simulation with jedec standard jesd51. esd caution
adl5565 data she et rev. d | page 10 of 28 pin c onfiguration and fun ction descriptions vip2 vip1 vin1 vin2 vo p enb l von vcom vcc vcc vcc vcc gnd gnd gnd gnd notes 1. exposed p addle is internal l y connect t o gnd and must be soldered t o a low impedance ground plane. 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 t o p view ad l 5565 09959-002 figure 2 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 vip2 balanced differential input. biased to vcom, typically ac - coupl ed. input for a v = 12 db gain, strapped to vip1 for a v = 15.5 db. 2 vip1 balanced differential input. biased to vcom, typically ac - coupled. input for a v = 6 db gain, strapped to vip2 for a v = 15.5 db. 3 vin1 balanced differential input. biased to vcom, t ypically ac - coupled. input for a v = 6 db gain, strapped to vin2 for a v = 15.5 db. 4 vin2 balanced differential input. biased to vcom, typically ac - coupled. input for a v = 12 db gain, strapped to vin1 for a v = 15.5 db. 5, 6, 7, 8 vcc positive supply. 9 v c o m common - mode voltage. a voltage applied to this pin sets the common - mode voltage of the input and output. typically decoupled to ground with a 0.1 f capacitor. with no reference applied, input and output common mode floats to midsupply (vcc/2). 10 von balanced differential output. biased to vcom, typically ac - coupled. 11 vop balanced differential output. biased to vcom, typically ac - coupled. 12 enbl enable. apply positive voltage (1.3 v < enb l < vcc) to activate device. 13, 14, 15, 16, exposed paddl e gnd ground. e xposed paddle is internally connected to gnd and must be soldered to a low impedance ground plane.
data sheet adl5565 rev. d | page 11 of 28 typical performance characteristics v s = 3.3 v, v cm = 1.65 v, r l = 200 ? differential, a v = 6 db, c l = 1 pf differential, f = 1 0 0 mhz, t a = 25c; parameters specified ac - coupled differential input and differential output, unless otherwise noted. ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 10 100 1000 10000 vo lt age gain (db) frequenc y (mhz) a v = 15db a v = 12db a v = 6db 09959-003 figure 3 . gain vs. frequency response for 200 ? differential load, a v = 6 db, a v = 12 db, and a v = 15.5 db, vpos = 3.3 v and vpos = 5 v, 25c ?20 ?15 ?10 ?5 0 5 10 15 20 10 100 10000 1000 volt age gain (db) frequenc y (mhz) ?40c +85c +25c +100c 09959-004 figure 4 . gain vs. frequency response for 200 ? differential load, a v = 6 db , four temperatures, vpos = 3.3 v, 25c 10 100 10000 1000 vo lt age gain (db) frequenc y (mhz) ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 ?40c +25c +85c +100c 09959-105 figure 5 . gain vs. frequency response for 200 ? differen tial load, a v = 6 db, four temperatures, vpos = 5 v, 25c 0 5 10 15 20 25 0 50 100 150 200 250 op1db (dbm) frequenc y (mhz) 09959-005 a v = 15.5db a v = 12db a v = 6db figure 6 . op1db vs. frequency at three gains, 25c, 200 ? differential load, vpos = 3.3 v 0 5 10 15 20 25 0 50 100 150 200 250 op1db (dbm) frequenc y (mhz) ?40c +25c +85c +100c 09959-006 figure 7 . op1db vs. frequency for 200 ? differen tial load , a v = 6 db, four temperatures, vpos = 3.3 v 0 2 4 6 8 10 12 14 16 18 10 100 1000 noise figure (db) frequenc y (mhz) 09959-007 a v = 6db a v = 12db a v = 15.5db figure 8 . noise figure vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db, vpos = 3.3 v
adl5565 data she et rev. d | page 12 of 28 0 2 4 6 8 10 12 14 16 18 10m 100m 1g noise figure (db) frequenc y (hz) a v = 6db a v = 12db a v = 15.5db 09959-008 figure 9 . noise figure vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db, vpos = 5 v 10 100 1000 frequenc y (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 noise spectra l densit y (nv/hz) a v = 6db a v = 12db a v = 15.5db a v = 6db a v = 12db a v = 15.5db 09959-009 figure 10 . noise spectral density vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db, vpos = 3.3 v and vpos = 5 v 0 10 20 30 40 50 60 0 50 100 150 200 250 300 350 400 450 500 oip3 (dbm) frequenc y (mhz) 5v, a v = 6db 5v, a v = 12db 5v, a v = 15.5db 3.3v, a v = 6db 3.3v, a v = 12db 3.3v, a v = 15.5db 09959-010 figure 11 . output third - or der intercept (oip3) at three gains, output level at 2 v p - p composite, r l = 200 ?, vpos = 3.3 v and vpos = 5 v 0 10 20 30 40 50 60 0 50 100 150 200 250 300 350 400 450 500 oip3 (dbm) frequenc y (mhz) 5v, ?40c 5v, +25c 5v, +85c 5v, +100c 3.3v, ?40c 3.3v, +25c 3.3v, +85c 3.3v, +100c 09959-0 1 1 figure 12 . output third - order intercept (oip3) vs. frequency, over temperature, output level at 2 v p - p composite, r l = 200 ?, a v = 6 db, vpos = 3.3 v and vpos = 5 v, four temperatures 0 10 20 30 40 50 60 70 0 1 2 3 4 5 6 7 8 9 10 oip3 (dbm) p out / t one (dbm) 3.3v, a v = 6db 3.3v, a v = 12db 3.3v, a v = 15.5db 5v, a v = 6db 5v, a v = 12db 5v, a v = 15.5db 09959-012 figure 13 . output third - order intercept (oip3) vs. power (p out ), frequency 100 mhz, a v = 15.5 db, vpos = 3.3 v and vpos = 5 v ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 imd3 (dbc) frequency (mhz) 09959-013 5v, a v = 6db 5v, a v = 12db 5v, a v = 15db 3.3v, a v = 6db 3.3v, a v = 12db 3.3v, a v = 15db figure 14 . output imd3 vs. frequency, output level at 2 v p - p composite, r l = 200 ?, vpos = 3.3 v and vpos = 5 v
data sheet adl5565 rev. d | page 13 of 28 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 imd3 (dbm) frequency (mhz) 09959-014 5v, ?40c 5v, +25c 5v, +85c 5v, +100c 3.3v, ?40c 3.3v, +25c 3.3v, +85c 3.3v, +100c figure 15 . imd3 vs. frequency, over temperature, output level at 2 v p - p composite, r l = 200 ?, a v = 6 db, vpo s = 3.3 v and vpos = 5 v, four temperatures 25 30 35 40 45 50 55 0 50 100 150 200 250 oip3 (dbm) frequenc y (mhz) 09959-015 a v = 5.3db a v = 10.3db a v = 13db figure 16 . single - ended oip3 vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 0 50 100 150 200 250 300 350 400 450 500 hd3 (dbc) hd2 (dbc) frequenc y (mhz) hd2, 3.3v, a v = 6db hd2, 3.3v, a v = 12db hd2, 3.3v, a v = 15.5db hd2, 5v, a v = 6db hd2, 5v, a v = 12db hd2, 5v, a v = 15.5db hd3, 3.3v, a v = 6db hd3, 3.3v, a v = 12db hd3, 3.3v, a v = 15.5db hd3, 5v, a v = 6db hd3, 5v, a v = 12db hd3, 5v, a v = 15.5db 09959-016 figure 17 . harmonic distortion (hd2/hd3) vs. frequency, output level at 2 v p - p composite, r l = 200 ?, vpos = 3.3 v and vpos = 5 v ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 0 50 100 150 200 250 300 350 400 450 500 hd3 (dbc) hd2 (dbc) frequenc y (mhz) hd2, 5v, ?40c hd2, 5v, +25c hd2, 5v, +85c hd2, 5v, +100c hd2, 3.3v, ?40c hd2, 3.3v, +25c hd2, 3.3v, +85c hd2, 3.3v, +100c hd3, 5v, ?40c hd3, 5v, +25c hd3, 5v, +85c hd3, 5v, +100c hd3, 3.3v, ?40c hd3, 3.3v, +25c hd3, 3.3v, +85c hd3, 3.3v, +100c 09959-017 figure 18 . harmonic distortion (hd2/hd3) vs. frequency, over temperature, output level at 2 v p - p composite, r l = 200 ?, a v = 6 db, vpos = 3.3 v and vpos = 5 v, four temperatures p out / t one (dbm) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?6 ?4 ?2 0 2 4 6 8 10 hd3 (dbc) hd2 (dbc) 3.3v, hd2 5v, hd2 3.3v, hd3 5v, hd3 09959-018 figure 19 . harmonic distortion v s. output power per tone , frequency = 100 mhz, r l = 200 ?, vpos = 3.3 v and vpos = 5 v ?120 ?100 ?80 ?60 ?40 ?20 0 1.0 1.5 2.0 2.5 3.0 hd2 and hd3 (dbc) vcom hd2, 5v hd3, 5v hd2, 3.3v hd3, 3.3v 09959-019 figure 20 . harmonic distortion (hd2/hd3) vs. vcom, a v = 6 db, vpos = 3.3 v and vpos = 5 v
adl5565 data she et rev. d | page 14 of 28 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 0 50 100 150 200 250 300 harmonic dis t ortion hd2, hd3 (dbc) hd2 a v = 5.3db hd2 a v = 10.3db hd2 a v = 13db hd3 a v = 5.3db hd3 a v = 10.3db hd3 a v = 13db frequenc y (mhz) 09959-020 figure 21 . single - ended harmonic distortion (hd2/hd3) vs. frequency, ch3 400mv/div 25gs/s 8:0g a ch3 832mv 1 3 50? ch1 70.4mv 2ns/div b w 09959-022 figure 22 . enbl time domain response 25gs/s ch1 340mv a ch2 10mv 1 ch2 1.025v 2ns/div 09959-023 figure 23 . large signal pulse response, a v = 15.5 db 0 10 20 30 40 50 60 70 80 90 10 100 1000 cmrr (db) frequenc y (mhz) 09959-021 figure 24 . common - mode rejection ratio (cmrr) vs. frequency 09959-200 800 0 100 200 300 400 500 600 700 0 200 400 600 800 1000 group delay (ps) frequency (mhz) figure 25 . group delay vs. frequency ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1000 reverse isol a tion (db) frequenc y (ghz) 09959-025 figure 26 . reverse isolation (s12) vs. frequency a v = 6 db
data sheet adl5565 rev. d | page 15 of 28 09959-201 300 280 260 240 220 200 180 160 140 120 100 80 60 3.0 2.5 2.0 1.5 1.0 0.5 0 10 100 1000 equivalent parallel input resistance () equivalent parallel input capacitance (pf) frequency (mhz) resistance capacitance figure 27 . s11 equivalent rlc parallel network, a v = 6 db 09959-202 20 18 16 14 12 10 8 6 4 2 0 10 1 2 3 4 5 6 7 8 9 0 10 100 1000 equivalent series output resistance () equivalent series output inductance (nh) frequency (mhz) resistance capacitance figure 28 . s22 equivalent rlc parallel network, a v = 6 db 60 65 70 75 80 85 ?40 ?20 0 20 40 60 80 100 i supply (ma) temper a ture (c) 5v 3.3v 09959-027 figure 29 . i supply vs. temperature, r l = 200 ?, a v = 6 db, vpos = 3.3 v and vpos = 5 v
adl5565 data sheet rev. d | page 16 of 28 circuit description basic structure the adl5565 is a low noise, fully differential amplifier/adc driver that can operate from 2.8 v to 5.2 v. it provides three gain options, 6 db, 12 db, and 15.5 db, without the need for external resistors and has wide bandwidths of greater than 6 ghz for all gains. differential input impedance is 200 for 6 db, 100 for 12 db, and 67 for 15.5 db. it has a differential output impedance of 10 . r l 1 / 2 r s 1 / 2 r s ac 100 ? 200 ? 0.1 f 0.1 f 200 ? 100 ? 50 ? 50 ? vip2 vip1 vin1 vin2 5 ? 5 ? + + 09959-032 figure 30. basic structure the adl5565 is composed of a fully differential amplifier with on-chip feedback and feed forward resistors. the two feedforward resistors on each input set this pin-strappable amplifier in three different gain configurations of 6 db, 12 db, and 15.5 db, and by using two external resistors, any gain from 0 db to 15.5 db can be realized. the amplifier is designed to provide high differential open-loop gain and an output common-mode circuit that enables the user to change the common-mode voltage from the vcom pin. the amplifier is designed to provide superior low distortion at frequencies up to and beyond 300 mhz with low noise and low power consumption from a 3.3 v power supply at 70 ma. the adl5565 is very flexible in terms of i/o coupling. it can be ac-coupled or dc-coupled at the inputs and/or the outputs within the specified input and output common-mode levels. the input of the device can be configured as single-ended or differential with similar third-order distortion performance. due to the internal connections between the inputs and outputs, an output common-mode voltage between 1.4 v and 1.8 v at 3.3 v and 1.4 v to 3 v at 5 v must be maintained for the best distortion. for a dc-coupled input, the input common mode should be between 1.2 v and 2 v at the 3.3 v supply, and 1.2 v to 3.8 v at the 5 v supply. the device has been characterized using 2 v p-p into a 200 ac-coupled output. if the inputs are ac-coupled, the input and output common-mode voltages are set by vcc/2 when no external circuitry is used. the adl5565 provides an output common-mode voltage set by vcom, which allows driving an adc directly without external components. although distortion is similar over the specified frequency range at both 3.3 v and 5 v, lower distortion results on the 5 v supply for signal swings larger than 2 v p-p.
data sheet adl5565 rev. d | page 17 of 28 applications informa tion basic connections figure 31 shows the basic connections for operating the adl5565 . a pply a voltage between 3 v and 5 v to the vcc pins , a nd decouple each supply pin with at least one low inductance , 0.1 f surface - mount ceramic capacitor, placed as close as possible to the device. also, decouple t he vcom pin (pin 9) using a 0.1 f capacitor. the gain of the part is determined by the pin - st rappable input configuration. when input a is applied to vip1 and input b is applied to vin1, the gain is 6 db (minimum gain, see equation 1 and equation 2). when input a is applied to vip2 and input b is applied to vin2, the gain is 12 db (middle gain). w hen input a is applied to both vip1 and vip2 and input b is applied to both vin1 and vin2, the gain is 15.5 db (maximum gain). pin 1 to pin 4, pin 10, and pin 11 are biased at 1/2 vcc above ground and can be dc - coupled (if within the specified input or out put common - mode voltage levels) or ac - coupled as shown in figure 31. to enable the adl5565 , the enbl pin must be pulled high. pulling the enbl pin low puts the adl5565 in sleep mode, reducing the current consumption to 5 ma at ambient . 1 2 3 4 1 1 12 10 9 5 6 7 8 15 16 14 13 vip2 vip1 vin1 vin2 vop enb l von vcom vcc vcc vcc vcc ac vcc gnd gnd gnd gnd adl5565 vcc balanced load r l 0.1f 0.1f 0.1f a b 0.1f 0.1f 0.1f 10f 0.1f r s /2 r s /2 balanced source 09959-033 figure 31 . basic connections
adl5565 data she et rev. d | page 18 of 28 input and output int erfacing the adl5565 can be configured as a dif ferential input to differential output driver, as shown in figure 32 . the r esistors, r1 and r2, combined with the etc1 - 1 - 13 balun transformer, provide a 50 input match for the three input impedances that change with the variable gain strapping. the input and output 0.1 f capacitors isolate the vcc/2 bias from the source and balanced load. the load should equal 200 ? to pr ovide the expected ac performance (see the specifications section and the typical performance characteristics section). 3v to 5v vip2 vip1 vin1 vin2 a b 50 ? ac r2 + + 0.1 f etc1-1-13 0.1 f + r1 + 0.1 f 0.1 f notes 1. for 6db gain (a v = 2), connect input a to vip1 and input b to vin1. 2. for 12db gain (a v = 4), connect input a to vip2 and input b to vin2. 3. for 15.5db gain (a v = 6), connect input a to both vip1 and vip2 and input b to both vin1 and vin2. r l 2 r l 2 09959-034 figure 32 . differe ntial input to differential output co nfiguration table 6 . differential termination values for figure 32 gain (db) r1 (?) r2 (?) 6 29 29 12 33 33 15.5 40.2 40.2 the differential gain of the adl5565 is dependent on the source impedance and load, as shown in figure 33. 100 ? 200 ? 200 ? 100 ? 50 ? 50 ? vip2 vip1 vin1 vin2 5 ? 5 ? r l ac 1 / 2 r s 1 / 2 r s 0.1 f + 0.1 f + 09959-035 figure 33 . differential input loading circuit the differential gain can be determined using the following formula. the values of r g for each gain configuration are shown in table 7 . l l g v r r r a + = 10 200 (1) in equation 1, r g is the gain setting resistor ( see figure 1 ) . table 7 . values of r g for differential gain gain (db) r g (?) 6 100 12 50 15.5 33.5 single - ended input to differential output the adl5565 can also be configured in a single - ended input to differential output driver, as shown in figure 34 . in this configuration, the gain of the part is reduced due to the application of the signal to only one side of the amplifier. the strappable gain values are listed in table 8 with the required terminations t o match to a 50 ? source using r1 and r2. the input and output 0.1 f capacitors isolate the vcc/2 bias from the source and the balanced load. the performance for this configuration is shown in figure 16 and figure 21. vip2 vip1 vin1 vin2 a b 50 ? ac r2 + + 0.1 f 0.1 f 0.1 f 3v to 5v + r1 notes 1. for 5.3db gain (a v = 1.84), connect input a to vip1 and input b to vin1. 2. for 10.3db gain (a v = 3.3), connect input a to vip2 and input b to vin2. 3. for 13db gain (a v = 4.5), connect input a to both vip1 and vip2 and input b to both vin1 and vin2. + 0.1 f r l 2 r l 2 09959-036 figure 34 . single - ended input to differential output configuration table 8 . single - ended termination values for figure 34 gain (db) r1 (?) r2 (?) 5.3 30 73 10.3 30 104 13 30 154 the single - ended gain configuration of the adl5565 is dependent on the source impedance and load, as shown in figure 35. r l 200 ? 200 ? vip2 vip1 vin1 vin2 5? 5? r s ac r2 + + 0.1 f 0.1 f 0.1 f 0.1 f + r1 + 2 r l 2 100 ? 100 ? 50 ? 50 ? 09959-037 figure 35 . singl e - ended input loading circuit
data sheet adl5565 rev. d | page 19 of 28 the single - ended gain can be determined using the following formula. the values of r g and r x for each gain configuration are shown in table 9 . l l x s x s s s g v r r r r r r r r r r r r r a + + + ? ? ? ? ? ? ? ? + + = 10 2 2 2 2 200 1 (2) in equation 2, r g is the gain setting resistor ( see figure 1 ) . table 9 . values of r g and r x for single - ended gain gain db r g 1 r x 5. 3 100 r2 || 158 2 10.3 50 r2 || 96 2 13 33.5 r2 || 74 2 1 r g is the gain setting res istor (s ee figure 1 ). 2 these values are based on a 50 ? input match. gain adjustment and interfacing the effective gain of the adl5565 can be reduced using a number of techniques. a matched attenuator network can reduce the effective gain; however, this requires the addition of a separate component that can be prohibitive in size and cost. instead, a simple voltage divider can be implemented using the combination of additional series resistors at the amplifier input an d the input impedance of the adl5565 , as shown in figure 36 . a pair of resistors is used to match to the impedan ce of the previous stage. 0.1 f 1 / 2 r shunt 1 / 2 r s 1 / 2 r s ac 0.1 f 1 / 2 r series vip1 vin2 vin1 vip2 1 / 2 r series 1 / 2 r shunt adl5565 09959-038 figure 36 . gain adjustment using a series resistor figure 36 shows a typical implementation of the divider concept that effectively reduces the gain by adding attenuation at th e input. for frequencies less than 100 mhz, the input impedance of the adl5565 can be modeled as a real 66 ?, 100 ?, or 200 ? resistance (differential) for maximum, middle, and minimum gains, r espectively. assuming that the frequency is low enough to ignore the shunt reactance of the input and high enough so that the reactance of moderately sized ac coupling capacitors can be considered negligible, the insertion loss, il, due to the shunt divide r can be expressed as ? ? ? ? ? ? ? ? + = g series g r r r db il log 20 ) ( (3) in equation 3, r g is the gain setting resistor ( see figure 1 ) . adjusted gain (db) = 6 db, 12 db, or 15.5 db gain C il (db) (4) the necessary shunt component, r shunt , to match to the source impedance, r s , can be expressed as g series s shunt r r r r + ? = 1 1 1 ( 5 ) in equation 5, r g is the gain setting resistor ( see figure 1 ) . the insertion loss and the resultant power gain for multiple shunt resistor values are summar ized in table 10 . the source resistance and input impedance need careful attention when using equation 3 , equation 4 , and equation 5 . the reactance of the input impedance of the adl5565 and the ac coupling capacitors must be considered before assuming that they make a negligible contribution. table 10. differential gain adjustment using series resistor gain db differential r g 4 r s dif ferential r series differential r sunt 5 0 1 200 50 200 57. 6 1 1 200 50 154 57.6 2 1 200 50 118 59 3 1 200 50 84.5 60.4 4 1 200 50 52.3 61.9 5 1 200 50 24.9 64.9 6 1 200 50 0 66.5 7 2 100 50 78.7 69.8 8 2 100 50 59 73.2 9 2 100 50 42.2 76.8 10 2 100 50 26.7 82.5 11 2 100 50 12.7 88.7 12 2 100 50 0 100 13 3 6 6.7 50 23.7 113 14 3 6 6.7 50 13.7 133 15.5 3 6 6.7 50 0 200 1 amplifier is configured for 6 db g ain s etting . 2 amplifier is configured for 12 db g ain s etting . 3 amplifier is configured for 15.5 db gain setting. 4 r g is the gain setting r esistor (s ee figure 1 ). 5 the resistor values are rounded to the nearest real resistor value.
adl5565 data sheet rev. d | page 20 of 28 adc interfacing the adl5565 is a high output linearity amplifier that is optimized for adc interfacing. there are several options available to the designer when using the adl5565 . figure 40 uses a wideband 1:1 transmission line balun followed by two 40 resistors in parallel with the three input impedances (which change with the gain selection of the adl5565 ) to provide a 50 differential impedance and provides a wideband match to a 50 source. the adl5565 is ac-coupled from the ad9467 to avoid common-mode dc loading. the 33 resistors improve the isolation between the adl5565 and any switching currents present at the analog-to-digital, sample-and-hold circuitry. the ad9467 input presents a 530 differential load impedance and requires a 2 v to 2.5 v differential input swing to reach full scale (vref = 1 v to 1.25 v). this circuit provides variable gain, isolation, and source matching for the ad9467. applying a full-scale, single-tone signal from the adl5565 , an sfdr of 91.9 dbc is realized (see figure 37). applying two half- scale signals from the adl5565 in a gain of 6 db, an sfdr of 86.4 dbc is achieved at 100 mhz (see figure 38). the bandwidth of the circuit in figure 40 is shown in figure 39. 0 15 0 3045607590105120 gain = 6db snr = 69.42dbc sfdr = 91.9dbc second = ?95.5dbc third = ?96.5dbc noise floor = ?115.6db amplitude (dbfs) frequency (mhz) ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 ?150 09959-049 figure 37. measured single-tone performance of the circuit in figure 40 for a 100 mhz input signal 2f2 ? f1 2f1 ? f2 f1 ? f2 2f2 ? f1 2f1 + f2 f1 + f2 0 15 0 3045607590105120 fundamental1 = ?7.034dbfs fundamental2 = ?7.053dbfs imd (2f1 ? f2) = ?90.677dbc imd (2f2 + f1) = ?92.101dbc noise floor = ?115.2db amplitude (dbfs) frequency (mhz) ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 ?150 09959-041 figure 38. measured two-tone performance of the circuit in figure 40 for a 100 mhz and 102 mhz input signals ? 5 ? 4 ? 3 ? 2 ? 1 0 0100 200 300 400 500 normalized (dbfs) frequency (mhz) 09959-042 figure 39. measured frequency response of the wideband adc interface depicted in figure 40 the wideband frequency response is an advantage in broad- band applications, such as predistortion receiver designs and instrumentation applications. however, by designing for a wide analog input frequency range, the cascaded snr performance is somewhat degraded due to high frequency noise aliasing into the wanted nyquist zone. 0.1f 40 ? 50 ? a c 0.1 f etc1-1-13 vin1 vip1 v ip2 a b vin2 40 ? adl5565 + + 0.1f 0.1f 33? vop von 33? + + ad9467 16-bit adc 16 vin+ vin? 09959-039 figure 40. wideband adc interfacing example featuring the ad9467
data sheet adl5565 rev. d | page 21 of 28 by designing a narrow b and - pass antialiasing filter between the adl5565 and the target adc, the output noise of the adl5565 outside of the intended nyqui st zone can be attenuated, helping to preserve the available snr of the adc. in general, the snr improves several decibels when including a reasonable order anti - alias ing filter. in this example, a low loss 1:1 input transformer is used to match the adl5565 balanced input to a 50 unbalanced source, resulting in minimum insertion loss at the input. figure 41 is optimized for driving some of analog devices popular adcs , such as the ad9467 . table 11 includes antialiasing filter component recommendations for popular if sampling frequencies . inductor l5 works in parallel with the on - ch ip adc input capacitance and a portion of the capacitance presented by c4 to form a resonant tank circuit. the resonant tank helps to ensure that the adc input looks like a real resistance at the target center frequency. the inductor , l5, shorts the adc in puts at dc, which introduces a zero into the transfer function. in addition, the ac coupling capacitors introduce additional zeros into the transfer function. the final overall frequency response takes on a band - pass characteristic, helping to reject noise outside of the intended nyquist zone. table 11 provides initial suggestions for proto - typing purposes. some empirical optimization may be needed to help compensate for actual pcb parasitics. 105? l5 105? ad9467 1nf l1 c2 l3 1nf l1 l3 c4 cml adl5565 4? 4? 09959-043 figure 41 . narrow - band if sampling solution for an adc application table 11 . interface filter recommendations for various if sampling frequencies center frequenc m 1 db bandwidth m 1 n c2 pf 3 n c4 pf 5 n 96 3 0 3.3 47 27 75 82 140 40 3.3 47 27 27 150 170 32 3.3 56 27 18 120 211 33 3.3 47 27 15 51
adl5565 data she et rev. d | page 22 of 28 layout consideration s high - q inductive drives and loads, as well as stray transmission line capacitance in combination with package parasitics, can potenti ally form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. if rf transmission lines connecting the input or output are used, design them such that stray capacitance at the input/output pins is minimized. in many board designs, the signal trace widths should be minimal where the driver/receiver is no more than one - eighth of the wave - length from the amplifier. this nontransmission line configuration requires that underlying and adjacent ground and low impeda nce planes b e dropped from the signal lines. 0.1f 0.1f 0.1f 0.1f adl5565 vip2 vip1 vin1 vop von vin2 r6 r5 r4 r3 r2 r1 r8 r7 r10 r9 etc1-1-13 etc1-1-13 spectrum analyzer 09959-044 figure 42 . general - purpose characterization circuit table 12 . gain setting and input termination components for figure 42 a v (db) r 1 (?) r2 (?) r3 (?) r4 (?) r5 (?) r6 (?) 6 29 29 open 0 0 open 12 33 33 0 open open 0 15.5 40.2 40.2 0 0 0 0 table 13 . output matching network for figure 42 r l (?) r7 (?) r8 (?) r9 (?) r10 (?) 200 84.5 84.5 34.8 34.8 adl5565 vip2 vip1 vin1 vop von vin2 r6 r5 r4 r3 r2 r1 port 1 port 3 port 2 port 4 r8 r7 r10 r9 09959-045 figure 43 . differential characterizatio n circuit using agilent e8357a four - port pna table 14 . gain setting and input termination components for figure 43 a v (db) r1 (?) r2 (?) r3 (?) r4 (?) r5 (?) r6 (?) 6 100 100 open 0 0 open 12 open open 0 open open 0 15.5 open open 0 0 0 0 table 15 . output matching network for figure 43 r l (?) r7 (?) r8 (?) r9 (? ) r10 (?) 200 50 50 open open
data sheet adl5565 rev. d | page 23 of 28 soldering informatio n and r ecommended pcb l and p attern figure 44 show s the recommended land pattern for the adl5565 . the adl5565 is contained in a 3 3 mm lfcsp package , which has an exposed ground paddle (epad) . this paddle is internally connected to the ground of the chip. to minimize thermal impedance and ensure elect rical performance , s older the paddle to the low impedance ground plane on the pcb . to further reduce thermal impedance, it is recommended that the ground planes on all layers under the paddle be stitched together with vias. for more information on land pat tern design and layout, refer to the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . this land pattern, on the adl5565 evaluation board, provides a measured thermal resistance ( ja ) of 6 0 c/w. to measure ja , the temperature at the top of the lfcsp package is found with an ir temperature gun. thermal simulation suggests a junctio n temperature 1.5c higher than the top of package temperature. with additional ambient temperature and i/o power measure - ments, ja could be determined. 36mils 12mils 59mils 59mils 122mils 19.7mils 10mils 09959-050 59mils figure 44 . recommended land pattern evaluation board figure 45 shows the schematic of the adl5565 evaluation board. the board is powered by a single supply in the 3 v to 5 v range. the power supply is decoupled by 10 f and 0.1 f capacitor s. table 16 details the various configuration options of the evaluation board. figure 46 and figure 47 show the component and circuit side layouts of the evaluation board. to re a lize the minimum gain (6 db into a 200 load), input 1 (vin1 and vip1) must be used by installing 0 resistors at r3 and r4, leaving r5 and r6 open. r1 and r2 must be 33.2 for a 50 input impedance. likewise, driving input 2 (vin2 and vip2) realizes t he middle gain (12 db into a 200 load) by installing 0 at r5 and r6 and leaving r3 and r4 open. r1 and r2 must be 50 for a 50 input impedance. for the maximum gain (15.5 db into a 200 load), both inputs are driven by installing 0 resistors at r 3, r4, r5, and r6. r1 and r2 are open for a 50 input impedance. the balanced input and output interfaces are converted to single ended with a pair of baluns (m/a - com etc1 - 1 - 13). the balun at the input, t1, provides a 50 ? single - ended - to - differential tr ansformation. the output balun, t2, and the matching components are configured to provide a 200 to 50 impedance transformation with an insertion loss of about 1 1 db. as an alternative, the input transformer, t1, can be replaced with one of the followin g transformers to provide a low loss balanced input to the adl5565 . ? 6 db gain configuration, mini - circuits tc4 - 1w+ ? 12 db gain configuration, mini - circuits, tc2 - 1t+ ? 15.5 db gain configuration, mini - circuits tc1.5 - 52t when using these alternative transformers, r1 and r2 are left open. replace c1 and c2 with 0 ? jumper s and add a 0.1 f capacitor to c12.
adl5565 data she et rev. d | page 24 of 28 c3 10f c4 0.1f c5 0.1f c6 0.1f c7 0.1f c8 0.1f c13 open c11 0.1f vpos r9 34.8 ? r11 open r15 open r14 0? j3 r10 34.8 ? r8 84.5 ? c10 0.01f c9 0.01f p1 t2 vcom agnd vpos gnd r7 84.5 ? enbl j4 open r12 open r13 0? j2 open adl5565 9 10 11 12 4 3 2 1 16 15 14 13 5 6 7 8 gnd gnd gnd gnd vcc vin1 vin2 vip2 vip1 von vcom enbl vop vcc vcc vcc c12 open j1 t1 r1 open r2 open r4 0? r3 0? r5 0? r6 0? c1 0.01f c2 0.01f 09959-046 figure 45 . evaluation board schematic table 16 . evaluation board configuration options component description default condition vpos, gnd ground and supply vector pins. vpos, gnd = installed c3, c4, c5, c6, c7, c11 power supply decoupling. the supply decoupling consists of a 10 f capacitor (c3) to ground. c4 to c7 are bypass capacitors. c11 ac couples vref to ground. c3 = 10 f (size d), c4, c5, c6, c7, c11 = 0.1 f (size 0402) j1, j2, r1, r2, r3, r4, r5, r6, r12, r13, c1, c2, c12, t1 input interface. the sma labeled j1 is the input. t1 is a 1 -to - 1 impedance ratio balun to transform a single - ended input into a balanced differential signal. removing r13 , installing r12 ( 0 ? ) , and installing an sma connector ( j2 ) allows driving from a differential source. c1 and c2 provide ac coupling. c12 is a bypass capacitor. r1 and r2 provide a differential 50 ? input termination. r3 to r6 are used to select the input for the pin - strappable gain. the m aximum gain is r3, r4, r5, r6 = 0 ? and r1 and r2 = open. the m iddle gain is r5 and r6 = 0 ? , r3 and r4 = open , and r1 and r2 = 50 ? . the m inimum gain is r3 and r4 = 0 ? , r5 and r6 = open , and r1 and r2 = 33.2 ? . j1 = installed, j2 = not installed, r1, r2 = open, r3, r4, r5, r6, r13 = 0 ? (size 0402), r12, = open, c1, c2 = 0.01 f (size 0402), c12 = op en, t1 = etc1 - 1 - 13 (m/a - com) j3, j4, r7, r8, r9, r10, r11, r14, r15 c9, c10, c13, t2 output interface. the sma labeled j3 is the output. t2 is a 1 - to - 1 impedance ratio balun to transform a balanced differential signal to a single - ended signal. removing r1 4, installing r15 (0 ? ), and installing an sma connector (j4) allows differential loading. c13 is a bypass capacitor. r7, r8, r9, and r10 are provided for generic placement of matching components. the evaluation board is configured to provide a 200 ? to 50 ? impedance transformation with an insertion loss of 17 db. c9 and c10 provide ac coupling . j3 = installed, j4 = not installed, r7, r8 = 84.5 ? (size 0402), r9, r10 = 34.8 ? (size 0402), r11, r15 = open (size 0402), r14 = 0 ? (size 0402 ) c9, c10 = 0.01 f (size 0402), c13 = open t2 = etc1 - 1 - 13 (m/a - com) enbl, p1, c8 device enable d . c8 is a bypass capacitor. when the p1 jumper is set toward the vpos label, the enbl pin is connected to the supply, enabling the device. in the opposite direction , toward the g nd label, the enbl pin is grounded, putting the device in power - down mode. enbl, p1 = installed, c8 = 0.1 f (size 0402) table 17 . differential values for figure 45 g ain (db) r1 ( ? ) r2 ( ? ) 6 29 29 12 33 33 15.5 open open table 18 . alternative differential input configuration for figure 45 g ain (db) r1 and r2 ( ? ) c12 ( f) c1 and c2 ( ?) t1 6 o pen 0.1 0 mini circuits tc4 -1w+ 12 o pen 0.1 0 mini circu its tc2 - 1t+ 15.5 o pen 0.1 0 mini circuits tc1.5 - 52t+
data sheet adl5565 rev. d | page 25 of 28 09959-047 figure 46 . layout of evaluation board, component side 09959-048 figure 47 . layout of evaluation board, circuit side
adl5565 data sheet rev. d | page 26 of 28 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.65 1.50 sq 1.45 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-26-2012-a figure 48. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-27) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adl5565acpz-r7 ?40c to + 85c 16-lead lead frame chip scale package [lfcsp_wq], 7 tape and reel cp-16-27 q1z adl5565-evalz evaluation board 1 z = rohs compliant part
data sheet adl5565 rev. d | page 27 of 28 notes
adl5565 data she et rev. d | page 28 of 28 notes ? 2011 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09959 - 0- 8/13(d)
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